Some lovely evidence in this Unsanity blog post and this mailing list post to support the idea that Apple's badly-named Intel laptop and the new iMac are not, in fact, the bee's knees.

Key points : SSE is balls compared to Altivec*, which doesn't bode well for any of the Pro apps (or any form of video playback, among other things). The Intel laptop has lost a couple of features, the Intel macs use EFI instead of the BIOS (that's actually Good, but it means I'll be paying a hell of a lot of attention to the state of VMWare, VPC and so forth) and last but not least, disk partition maps for bootable volumes are Different (read: incompatible)- so while your binaries might be universal, your / isn't. Good job Apple.

Oh, and there's no Classic support (shock.), and none of the major productivity software is shipping Universal Binaries yet- so these things aren't going to be all that useful for at least another six months to a year.

In other words the platform is now a real mess. But hey, new iApps. Look at the shiny, try not to listen to the massive sucking sound coming from Cupertino.

As usual, the hardware will eventually "catch up" - and maybe in ten or fifteen years it'll be as responsive as it was in 1998. Until then, the world of computing is becoming progressively less of an "oooh, what next?!" and more of a "grit your teeth and bear it." - at least until the dust clears.

Some of the more vocal developer commentary is along the lines of "we'd rather be adding feejur support instead of dicking around with SSE optimization" - clearly The Mothership has convinced developers that performance isn't one of the bullet-points that people are looking for these days. Bummer.

* See the mailing list link if you think I'm being my usual opinionated self. SSE is a 1999 sequel to MMX, while Altivec (developed '96-'98 at Apple) is an in-house thing.

From the wikipedia entry:

Altivec as implemented on the G4 and G5 PPC processors can perform 8 32-bit FLOPS per cycle and SSE as implemented processors by AMD and Intel can perform only 4 32-bit FLOPS per cycle (x86s are also capable of 2 64-bit FLOPS per cycle using SSE-2, whereas AltiVec is not). The obvious implication is that SSE would need a clock 2 times the frequency of Altivec to perform the same number of FLOPS per second.